Semiconductor packages are designed to seal and protect chip(s) encapsulated inside where the chip carrier has been gradually changed from leadframes to wiring substrates. However, leadframes still serve their purposes for low-pin count products and for severe environmental requirements such as TSOP 48 for NAND flash. As the chip dimension and the number of stacked chips increases related to the package dimension, more defeats are shown up during molding processes such as entrapment of bubbles during molding processes and fixing of leads during wire bonding processes.
Furthermore, conventional leadframe-type semiconductor packages are applied by the original applicant which are disclosed in US Patent Publication Number 2010/0122454 A1 entitled “METHOD FOR FORMING AN ISOLATED INNER LEAD FROM A LEADFRAME” and in US Patent Publication Number 2010/0127362 A1 entitled “SEMICONDUCTOR PACKAGE HAVING ISOLATED INNER LEAD” where chips are attached on the leads of a leadframe, however, the pad side of the chip is lack of the wire-bonding support from the die pad of the leadframe.